System and method for map detector for symbol based error correction codes

ABSTRACT

A system for decoding data includes a symbol based error correction code device. The error correction code device includes a channel detector configured to generate probability mass function (PMF) information. The error correction code device further includes a decoder coupled to the channel detector. The decoder is configured to use the PMF information from the channel detector to perform an error correction code operation. The decoder also is configured to generate PMF information. The channel detector is configured to receive extrinsic PMF information in a turbo equalization scheme.

CROSS-REFERENCE TO RELATED APPLICATION(S) AND CLAIM OF PRIORITY

The present application is related to U.S. Provisional Patent No. 61/245,996, filed Sep. 25, 2009, entitled “SYSTEM AND METHOD FOR MAP DETECTOR FOR Q'ARY LOW DENSITY CHECK PARITY CODES”. Provisional Patent No. 61/245,996 is assigned to the assignee of the present application and is hereby incorporated by reference into the present application as if fully set forth herein. The present application hereby claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent No. 61/245,996.

TECHNICAL FIELD OF THE INVENTION

The present application relates generally to channel detection/error correction code decoding systems and, more specifically, to a system and method for decoding data with a symbol based error correction code, such as a Q'ary LDPC Code.

BACKGROUND OF THE INVENTION

Several communications systems, including magnetic recording channels, experience inter-symbol-interference (ISI). In general, a channel detector is employed to recover ISI channel inputs. Usually, a maximum-a-posteriori (MAP) detector or soft output Viterbi algorithm (SOVA) is used as the channel detector. Both detectors compute soft information (likelihood information) which might be used by an outer error correction code.

In order to improve reliability of communication systems, conventional systems employ different error correction codes. Among these, a Low Density Parity Check (LDPC) code is an excellent error correction code (ECC). The LDPC codes can be applied to a variety of communication systems, including magnetic recording channels.

SUMMARY OF THE INVENTION

A system for decoding data is provided. The system includes a symbol based error correction code device. The system includes a channel detector configured to generate probability mass function (PMF) information. The system further includes a decoder coupled to the channel detector. The decoder is configured to use the extrinsic PMF information from the channel detector to perform an error correction code operation. The decoder also is configured to generate extrinsic PMF information for use in the channel detector. Optionally, one may use a symbol based interleaver between the channel detector and ECC decoder.

A magnetic drive apparatus for use in a data decoding system is provided. The magnetic drive apparatus includes a channel detector configured to recover inter-symbol-interference channel inputs and generate a first set of PMF information based on the channel outputs. The magnetic drive apparatus also includes an ECC decoder configured to perform a symbol-based error correction code operation. The detector further is configured to output the PMF information to the ECC decoder. The ECC decoder is configured to use the PMF information to perform an error correction code operation.

A method for decoding data is provided. The method includes receiving inter-symbol-interference channel outputs. A channel detector generates PMF information (symbol probabilities) based at least in part on the received channel outputs. The method also includes performing a symbol based error correction code operation using the PMF information from the channel detector; and generating full PMF information from the first PMF information for used in the channel detector.

Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts:

FIG. 1 illustrates a binary (bit-based) error correction code (ECC) device according to the present disclosure;

FIGS. 2A through 2B illustrate symbol-based iterative devices according to embodiments of the present disclosure;

FIG. 3 illustrates a write path according to embodiments of the present disclosure;

FIG. 4 illustrates a four-state trellis diagram according to embodiments of the present disclosure;

FIG. 5 illustrates a four-state trellis for a half rate detector according to embodiments of the present disclosure;

FIG. 6 illustrates two stages of a four-state trellis diagram according to embodiments of the present disclosure;

FIG. 7 illustrates a half rate four state detector trellis according to embodiments of the present disclosure;

FIG. 8 illustrates a process for error correction coding according to embodiments of the present disclosure; and

FIGS. 9A through 9B illustrate devices capable of error correction decoding according to embodiments of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1 through 9, discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged system.

Properly designed symbol-based LDPC codes (Q'ary LDPC or “QLDPC” codes), can outperform a similar rate binary LDPC code over perpendicular magnetic channels at the expense of increased encoder and decoder complexity. Accordingly, symbol based ECCs can be utilized in multiple applications for several communications systems for their superior error correction capabilities. For example, the symbol based ECC can be included in a device that reads data from a magnetic communication medium.

FIG. 1 illustrates a binary (bit-based) LDPC based ECC device according to the present disclosure. The ECC device 100 shown in FIG. 1 is for illustration only. Other embodiments could be used without departing from the scope of this disclosure.

The ECC device 100 includes a channel detector 105, such as a MAP or SOVA detector. The output of the channel detector 105 is input into a bit-based de-interleaver (inverse interleaver) 110. The bit-based de-interleaver 110 outputs log likelihood ratios (LLRs) to a soft decision decoder 115, such as an LDPC decoder. The output of the soft decision decoder 115 is input to a bit-based interleaver 130.

Soft decision decoders of bit based error correction codes require the LLRs from the channel detector 105. Similarly, soft decision decoders 220 (described in more detail herein below with respect to FIGS. 2A and 2B) of symbol based codes, including QLDPC codes, require symbol probabilities referred to as a probability mass function (PMF). For example, assuming three-bit symbols (m: symbol size), the PMF of the symbol represents the probabilities of the Q'ary symbol x_(i) (i^(th) symbol), taking each of the eight (8) possible bit combinations as shown in Equation 1: PMF(x _(i))={Pr(x _(i) =f _(j));f _(j) εGF(q)}.  [Eqn. 1].

Therefore, according to equation 1, for three-bit symbols, PMF(x_(i)) is a 1×8 vector.

Traditional MAP and SOVA detectors compute the bit LLRs from which it is possible to extract the probabilities of each individual bit. When using a bit based interleaver 110 between the channel detector 105 and soft decision decoder 115 (such as an LDPC decoder), consecutive bits in the decoder domain will be independent. When bits forming a symbol are not correlated, the PMF entries can be computed according to Equation 2 by taking the product of the bit probabilities associated with the particular GF(q) symbol:

$\begin{matrix} {{{PMF}\left( x_{i} \right)} = {\left\{ {{\prod\limits_{k = 0}^{m - 1}{\Pr\left( {x_{{i \cdot m} + k} = f_{j}^{k}} \right)}};{f_{j} \in {{GF}\left( {q = 2^{m}} \right)}}} \right\}.}} & {\left\lbrack {{Eqn}.\mspace{14mu} 2} \right\rbrack.} \end{matrix}$

In Equation 2, f_(j) ^(k) represents k'th bit of symbol f_(j). For example, assuming 2 bit symbols, the PMF for i=0:

$\begin{matrix} {{{PMF}\left( x_{0} \right)} = {\begin{pmatrix} {\Pr\left( {\left\lbrack {x_{0}x_{1}} \right\rbrack = \lbrack 00\rbrack} \right)} \\ {\Pr\left( {\left\lbrack {x_{0}x_{1}} \right\rbrack = \lbrack 01\rbrack} \right)} \\ {\Pr\left( {\left\lbrack {x_{0}x_{1}} \right\rbrack = \lbrack 10\rbrack} \right)} \\ {\Pr\left( {\left\lbrack {x_{0}x_{1}} \right\rbrack = \lbrack 11\rbrack} \right)} \end{pmatrix} = {\begin{pmatrix} {{\Pr\left( {x_{0} = 0} \right)} \cdot {\Pr\left( {x_{1} = 0} \right)}} \\ {{\Pr\left( {x_{0} = 0} \right)} \cdot {\Pr\left( {x_{1} = 1} \right)}} \\ {{\Pr\left( {x_{0} = 1} \right)} \cdot {\Pr\left( {x_{1} = 0} \right)}} \\ {{\Pr\left( {x_{0} = 1} \right)} \cdot {\Pr\left( {x_{1} = 1} \right)}} \end{pmatrix}.}}} & \left\lbrack {{Eqn}.\mspace{14mu} 3} \right\rbrack \end{matrix}$

Although computing the PMF by multiplying the bit probabilities is simple and trivial, it is not optimal and does not lead to very good performance. The problems are as follows:

Consecutive bit errors can result when the channel detector 115 fails. These consecutive errors are usually +−+ . . . error events. That is, for the input sequence of {010} the detector delivers {101}. These type or error events are also called “Nyquist” error events.

The existence of the error events also implies that the bit errors are correlated. Binary codes, however, are unable to take this error event information into account. Furthermore, the LDPC soft decision decoder 115 assumes that the bits participating in a parity check equation are not correlated, which can be achieved by using a combination of parity check matrix design and bit interleaving. Clearly, this approach destroys the error events information.

Conversely, symbol based codes can take into account the error event information in the decoding process. The logical way of using the error event information for symbol based decoding is to pass this information via the PMFs. That is, the symbol probabilities corresponding to error events should have higher probabilities. Assuming GF(8), for the case of a three-bit Nyquist error event, the PMF entries for ‘010’ and ‘101’ should have similar and high probabilities and the remaining PMF entries should have very low probabilities. Therefore, it is important that the method of computing the PMFs should reflect the error event information.

In some example, PMF is computed by multiplying individual bit probabilities. If the detector is not sure about a particular decision or the decision is erroneous, usually the magnitude of the LLR associated with that bit is very close zero, implying that the probabilities of the bit taking the value of ‘0’ or ‘1’ are almost the same. For example, assume the detector includes three consecutive bit errors (such as ‘010’ detected as ‘101’) and associated bit probabilities are {0.51, 0.51, 0.51}. In this example, if the PMF is computed by multiplication for GF(8), the eight PMF entries will be approximately ‘0.125’, implying that all eight GF(8) symbols are equally likely. Therefore, computing the PMFs by multiplying individual bit probabilities destroys the error event information.

As such, a first problem occurs when computing the PMFs from the channel detector in such a way that the error event information is preserved in the PMF. Furthermore, this computation should not increase the complexity of the channel detector and it should not require extensive changes in the existing systems.

The second problem occurs when an iterative detection/decoding system is adapted. For this case, the extrinsic information is exchanged between the detector and the decoder. The solution to the first problem addresses computing the extrinsic PMF information from the channel detector for use in the symbol based ECC decoder that also computes PMFs. Therefore, the second problem is how to use the extrinsic PMF information from the symbol based ECC decoder at the channel detector. The channel detector 105 (such as traditional MAP or SOVA channel detectors) accepts binary extrinsic LLR information. One trivial solution to this problem is to compute the LLR information from PMFs. This approach, however simple, does not deliver very good performance and limits the potential gains of turbo equalization.

FIGS. 2A through 2B illustrate symbol-based iterative devices according to embodiments of the present disclosure. The embodiments of the symbol-based iterative devices 200 shown in FIGS. 2A and 2B are for illustration only. Other embodiments could be used without departing from the scope of this disclosure.

The symbol-based iterative device 200 can be any symbol based device, such as a Q'ary iterative device. The symbol-based iterative device 200 includes a channel detector 205, such as a MAP or SOVA detector. In some embodiments, channel detector 205 computes LLRs. PMFs are computed from LLRs 210 and computed PMFs optionally interleaved through an inverse symbol interleaver 215 and then fed into the symbol based ECC decoder 220. The decoder computes PMFs and from the symbol interleaved PMFs 225, LLRs are computed 230 for use in the detector as extrinsic a-priori information. In the example illustrated in FIG. 2A, the inverse symbol interleaver 215 is optional. In FIG. 2B, channel detector 205 is configured to produce PMFs. These PMFs are, optionally, inverse interleaved through a symbol based interleaver 210 and passed to the symbol-based decoder 220 as an input. The output PMFs of the symbol-based decoder 220 can be input to a symbol based interleaver 225. Additionally, the output of the symbol based interleaver 215 is used in the channel detector 205 that is configured to use PMF information as the a-priori information as opposed to conventional channel detectors that require LLRs for a-priori information. In FIGS. 2A and 2B, the channel detector 205 and the symbol-based ECC decoder 220 exchanges only extrinsic information.

In some embodiments, the PMF from the symbol-based ECC decoder 220 can be converted back into LLR format for used by the channel detector 205 in the next iteration by PMF-to-LLR conversion 230. In some embodiments, the PMF to LLR conversion block 230 is not included. The PMF to LLR conversion can be avoided if the decoder interleaved PMF entries are combined with branch metric computation at the channel detector 205.

FIG. 3 illustrates a write path according to embodiments of the present disclosure. The embodiment shown in FIG. 3 is for illustration only. Other embodiments could be used without departing from the scope of this disclosure.

The write path 300 includes a bit-to-symbol conversion block 305, user symbols de-interleaver block 310, an encoding block 315 (such as a QLDPC encoder), an encoded symbols interleaver block 320, and a symbol-to-bit conversion block 325 coupled to the channel 330.

Referring back to FIG. 2, the channel detector 205 is configured to generate PMF for input into the soft decoder 220. The channel detector 205, such when implemented using a MAP algorithm (hereinafter referred to as MAP detector 205), is configured to perform a PMF computation for MAP or max-log-MAP detector. Given a transmitted sequence of m bits u=[u₁, . . . ,u_(m)] over an ISI channel affected by AWGN noise and a received sequence y=[y₁, . . . ,y_(m)], the MAP detector 205 computes the LLR of bit u_(t) which is defined according to Equation 4:

$\begin{matrix} {{{LLR}\left( u_{t} \right)} = {\log{\frac{\Pr\left( {u_{t} = \left. 0 \middle| \underset{\_}{y} \right.} \right)}{\Pr\left( {u_{t} = \left. 1 \middle| \underset{\_}{y} \right.} \right)}.}}} & \left\lbrack {{Eqn}.\mspace{14mu} 4} \right\rbrack \end{matrix}$

Given an N state trellis, the probability of a bit conditioned to the received noisy message can be computed by summing the probability over all valid transitions associated with the transitions bit x:

$\begin{matrix} {{{\Pr\left( {u_{t} = x} \right)} = {\sum\limits_{S_{t - 1}}{\sum\limits_{S_{t}}{{\Pr\left( {S_{t - 1},\left. S_{t} \middle| \underset{\_}{y} \right.,{u_{t} = x}} \right)} \cdot {\Pr\left( {S_{t - 1},S_{t},{u_{t} = x}} \right)}}}}},\mspace{20mu}{x \in {\left\{ {0,1} \right\}.}}} & \left\lbrack {{Eqn}.\mspace{11mu} 5} \right\rbrack \end{matrix}$

If there is no transition between S_(t−1) and S_(t) caused by transition bit x, then P(S_(t−1),S_(t),u_(t)=x)=0. If S_(t−1),_(t) ^(x) is used to represent the set of all valid transitions between S_(t−1) and S_(t) caused by transition bit x, the above equation can be simplified as Equation 6:

$\begin{matrix} {{\Pr\left( {u_{t} = x} \right)} = {\frac{1}{\Pr\left( \underset{\_}{y} \right)}{\sum\limits_{S_{{t - 1},t}^{x}}{{\Pr\left( {\underset{\_}{y},S_{{t - 1},t}^{x}} \right)}.}}}} & \left\lbrack {{Eqn}.\mspace{14mu} 6} \right\rbrack \end{matrix}$

Using the notation illustrated in Equation 7: y =(y ₁ ^(t−1) ,y _(t) ,y _(t+1) ^(m)) y ₁ ^(t−1)=(y ₁ , . . . , y _(t−1)) y _(t+1) ^(m)=(y _(t+1) , . . . , y _(m))  [Eqn. 7]; the chain rule of probabilities; and the Markov property of the ISI channel, the join probability can be computed as in Equation 8:

$\begin{matrix} \begin{matrix} {{\Pr\left( {\overset{\_}{y},S_{{t - 1},t}^{x}} \right)} = {{\Pr\left( {y_{1}^{t - 1},y_{t},y_{t + 1}^{m},S_{{t - 1},t}^{x}} \right)} =}} \\ {= {{\Pr\left( {y_{1}^{t - 1},S_{t - 1}^{x}} \right)} \cdot {\Pr\left( {y_{t},\left. S_{t}^{x} \middle| y_{1}^{t - 1} \right.,S_{t - 1}^{x}} \right)} \cdot}} \\ {\Pr\left( {\left. y_{t + 1}^{m} \middle| y_{1}^{t - 1} \right.,y_{t},S_{t - 1}^{x},S_{t}^{x}} \right)} \\ {= {{\Pr\left( {y_{1}^{t - 1},S_{t - 1}^{x}} \right)} \cdot {\Pr\left( {y_{t},\left. S_{t}^{x} \middle| S_{t - 1}^{x} \right.} \right)} \cdot}} \\ {{\Pr\left( y_{t + 1}^{m} \middle| S_{t}^{x} \right)}.} \end{matrix} & \left\lbrack {{Eqn}.\mspace{11mu} 8} \right\rbrack \end{matrix}$

In Equation 8, states S_(t−1) ^(x) and S_(t) ^(x) represent the beginning and the end states of the transition caused by transition bit u_(t)=x. Additionally, the values α, β and γ are defined by Equations 9A-9C: α_(t−1)(S _(t−1) ^(x))=Pr(y ₁ ^(t−1) ,S _(t−1) ^(x))  [Eqn. 9A]; β_(t)(S _(t) ^(x))=Pr(y _(t+1) ¹ |S _(t) ^(x))  [Eqn. 9B]; γ_(t) ^(x)(S _(t−1) ^(x) ,S _(t) ^(x))=Pr(y _(t) ,S _(t) ^(x) |S _(t−1) ^(x))  [Eqn. 9C].

Forward variable α and backward variable β can be computed recursively using the chain rule of probabilities and the Markov property of the ISI channel as in Equations 10A and 10B:

$\begin{matrix} {{{{\alpha_{t}\left( S_{t}^{x} \right)} = {\sum\limits_{S_{t - 1}^{x}}{{\alpha_{t - 1}\left( S_{t - 1}^{x} \right)} \cdot {\gamma_{t}\left( {S_{t - 1}^{x},S_{t}^{x}} \right)}}}};}{and}} & \left\lbrack {{{Eqn}.\mspace{14mu} 10}A} \right\rbrack \\ {{\beta_{t}\left( S_{t}^{x} \right)} = {\sum\limits_{S_{t + 1}^{x}}{{\beta_{t + 1}\left( S_{t + 1}^{x} \right)} \cdot {{\gamma_{t + 1}\left( {S_{t}^{x},S_{t + 1}^{x}} \right)}.}}}} & \left\lbrack {{{Eqn}.\mspace{14mu} 10}B} \right\rbrack \end{matrix}$

The well known branch metric γ can be computed assuming a Gaussian noise probability density function (pdf). Further, Equations 4, 6, 8 and 9A-9 can be re-written as Equation 11:

$\begin{matrix} {{{LLR}\left( u_{t} \right)} = {\log{\frac{\sum\limits_{S_{t - 1}^{0}}{\sum\limits_{S_{t}^{0}}{{\alpha_{t - 1}\left( S_{t - 1}^{0} \right)} \cdot {\gamma_{t}\left( {S_{t - 1}^{0},S_{t}^{0}} \right)} \cdot {\beta_{t}\left( S_{t}^{0} \right)}}}}{\sum\limits_{S_{t - 1}^{1}}{\sum\limits_{S_{t}^{1}}{{\alpha_{t - 1}\left( S_{t - 1}^{1} \right)} \cdot {\gamma_{t}\left( {S_{t - 1}^{1},S_{t}^{1}} \right)} \cdot {\beta_{t}\left( S_{t}^{1} \right)}}}}.}}} & \left\lbrack {{Eqn}.\mspace{14mu} 11} \right\rbrack \end{matrix}$

Equation 11 can be further simplified by observing that for a given state S_(t−1) ^(x) and input u_(t)=x, only the state S_(t) ^(x)=f(S_(t−1) ^(x),x) can be reached in the trellis. Therefore, Equation 11 can be rewritten by removing the summation over S_(t) ^(x) as Equation 12:

$\begin{matrix} {{{LLR}\left( u_{t} \right)} = {\log{\frac{\sum\limits_{S_{t - 1}^{0}}{{\alpha_{t - 1}\left( S_{t - 1}^{0} \right)} \cdot {\gamma_{t}\left( {S_{t - 1}^{0},{f\left( {S_{t - 1}^{0},0} \right)}} \right)} \cdot {\beta_{t}\left( S_{t}^{0} \right)}}}{\sum\limits_{S_{t - 1}^{1}}{{\alpha_{t - 1}\left( S_{t - 1}^{1} \right)} \cdot {\gamma_{t}\left( {S_{t - 1}^{1},{f\left( {S_{t - 1}^{1},1} \right)}} \right)} \cdot {\beta_{t}\left( S_{t}^{1} \right)}}}.}}} & \left\lbrack {{Eqn}.\mspace{14mu} 12} \right\rbrack \end{matrix}$

This also is a well known LLR expression of the BCJR (MAP) algorithm in probability domain.

The summation term in the numerator and the denominator of Equation 12, is given by Equation 13: T _(t−1,t) ^(x)=α_(t−1)(S _(t−1) ^(x))·γ_(t)(S _(t−1) ^(x) ,f(S _(t−1) ^(x) ,x))·β_(t)(S _(t) ^(x)), for xε{0,1}  [Eqn. 13].

Equation 13 represents the probability of moving from state S_(t−1) ^(x) to state S_(t) ^(x) with transition bit x given the received noisy channel output sequence y. For this transition, the branch metric will be γ_(t)(S_(t−1) ^(x),f(S_(t−1) ^(x),0)). The transition from state S_(t−1) ^(x) to state S_(t) ^(x) via transition bit x also represents a data pattern.

FIG. 4 illustrates a four-state trellis diagram according to embodiments of the present disclosure. The embodiment of the trellis diagram shown in FIG. 4 is for illustration only and other embodiments could be used without departing from the scope of this disclosure.

In the trellis 400, the transitions caused by u_(t)=0 and u_(t)=1 are represented by dashed and solid lines respectively. Furthermore, in the state representation, the right most bit is the most current bit. Some of the different data patterns associated with different transitions are:

Transition from 00 to 00→pattern (t−2,t−1,t)=000

Transition from 11 to 10→pattern (t−2,t−1,t)=110

Transition from 01 to 10→pattern (t−2,t−1,t)=010

It is noted that, if all transitions are considered, all possible 3 bit patterns result.

The trellis 400 is well suited for a full rate implementation, which only processes one trellis stage at a time. For a half rate implementation, two trellis stages are processed at the same time, resulting in four incoming paths for each destination state. This case is illustrated in the trellis diagram shown in FIG. 5.

Each transition corresponds to two trellis stages. Therefore, four incoming paths exist for each destination state. For example, a transition occurs from state ‘11’ to state ‘00’ via state ‘10’ with transition bits ‘00.’ Similarly, the transition from state ‘00’ to state ‘11’ is via state ‘01’ with transition bits ‘11.’

FIG. 6 illustrates two stages of a four-state trellis diagram according to embodiments of the present disclosure. FIG. 6 shows the two stages of a four state trellis which are merged into a single instance for a half rate detector. Some of the different data patterns associated with different transitions for a 4-state trellis using half rate implementation:

Transition from 11 to 00 via 10→pattern (t−3,t−2,t−1,t)=1100 (transition bits=00)

Transition from 10 to 00 via 00→pattern (t−3,t−2,t−1,t)=1000 (transition bits=00)

Transition from 01 to 10 via 11→pattern (t−3,t−2,t−1,t)=0110 (transition bits=10)

Considering two stages at a time for half rate (½) implementation, the data patterns are four bits. Similarly, for a ⅓ rate implementation, the data patterns associated with three consecutive transitions will be five bits. For quarter rate (¼) implementation, the data patterns will be six bits. Formulating the previously mentioned relation as follows: For 2^(n) state trellis with 1/k rate implementation, the length of the data patterns associated with the transitions will be (n+k) and the transitions cover all possible length (n+k) data patterns.

Since each transition in the trellis 600 represents a data pattern, the MAP detector 205 uses Equation 7 to compute the data pattern probability. Since a single stage of the trellis 600 is involved in creating the transition data pattern, the probability of the data pattern is formed by transitioning from S_(t−1) to S_(t) with transition bit u_(t)=x according to Equation 14: Pr(S _(t−1) ,S _(t) ,u _(t) =x)=α_(t−1)(S _(t−1))·γ_(t)(S _(t−1) ,f(S _(t−1) ,x))·β_(t)(S _(t)), for xε{0,1}  [Eqn. 14].

For 1/k rate implementation, since k trellis stages are involved, the probability of data pattern formed by making the transition from state S_(t−k) to S_(t) with k transition bits {u_(t−k+1), . . . ,u_(t)} is given Equation 15:

$\begin{matrix} {{\Pr\left( {S_{t - k},S_{t},u_{t - k + 1},\ldots\mspace{14mu},u_{t}} \right)} = {{\alpha_{t - k}\left( S_{t - k} \right)} \cdot \left( {\prod\limits_{z = 0}^{k - 1}{\gamma_{t}\left( {S_{t - k + z},{f\left( {S_{t - k + z},u_{t - k + 1 + z}} \right)}} \right)}} \right) \cdot {{\beta_{t}\left( S_{t} \right)}.}}} & \left\lbrack {{Eqn}.\mspace{14mu} 15} \right\rbrack \end{matrix}$

At a given time instant t, the PMF entries for m bit symbols give the probabilities for all 2^(m) possible binary combinations. Since the transitions correspond to data patterns, the data pattern probabilities can be used to compute the PMFs. For example, for a four state trellis full rate implementation (k=1), the PMFs for three bit symbols are computed as:

$\begin{matrix} \begin{matrix} {{{PMF}\left( S_{{({t - 1})}/m} \right)} = \begin{Bmatrix} {{{PMF}(000)}_{t} = {\Pr\left( {\left\lbrack {u_{t - 2}u_{t - 1}u_{t}} \right\rbrack = \lbrack 000\rbrack} \right)}} \\ {{{PMF}(001)}_{t} = {\Pr\left( {\left\lbrack {u_{t - 2}u_{t - 1}u_{t}} \right\rbrack = \lbrack 001\rbrack} \right)}} \\ {{{PMF}(010)}_{t} = {\Pr\left( {\left\lbrack {u_{t - 2}u_{t - 1}u_{t}} \right\rbrack = \lbrack 010\rbrack} \right)}} \\ {{{PMF}(011)}_{t} = {\Pr\left( {\left\lbrack {u_{t - 2}u_{t - 1}u_{t}} \right\rbrack = \lbrack 011\rbrack} \right)}} \\ {{{PMF}(100)}_{t} = {\Pr\left( {\left\lbrack {u_{t - 2}u_{t - 1}u_{t}} \right\rbrack = \lbrack 100\rbrack} \right)}} \\ {{{PMF}(101)}_{t} = {\Pr\left( {\left\lbrack {u_{t - 2}u_{t - 1}u_{t}} \right\rbrack = \lbrack 101\rbrack} \right)}} \\ {{{PMF}(110)}_{t} = {\Pr\left( {\left\lbrack {u_{t - 2}u_{t - 1}u_{t}} \right\rbrack = \lbrack 110\rbrack} \right)}} \\ {{{PMF}(111)}_{t} = {\Pr\left( {\left\lbrack {u_{t - 2}u_{t - 1}u_{t}} \right\rbrack = \lbrack 111\rbrack} \right)}} \end{Bmatrix}} \\ {= {\begin{Bmatrix} {{\alpha_{t - 1}(00)} \cdot {\gamma_{t}\left( {00,00} \right)} \cdot {\beta_{t}(00)}} \\ {{\alpha_{t - 1}(00)} \cdot {\gamma_{t}\left( {00,01} \right)} \cdot {\beta_{t}(01)}} \\ {{\alpha_{t - 1}(01)} \cdot {\gamma_{t}\left( {01,10} \right)} \cdot {\beta_{t}(10)}} \\ {{\alpha_{t - 1}(01)} \cdot {\gamma_{t}\left( {01,11} \right)} \cdot {\beta_{t}(11)}} \\ {{\alpha_{t - 1}(10)} \cdot {\gamma_{t}\left( {10,00} \right)} \cdot {\beta_{t}(00)}} \\ {{\alpha_{t - 1}(10)} \cdot {\gamma_{t}\left( {10,01} \right)} \cdot {\beta_{t}(01)}} \\ {{\alpha_{t - 1}(11)} \cdot {\gamma_{t}\left( {11,10} \right)} \cdot {\beta_{t}(10)}} \\ {{\alpha_{t - 1}(11)} \cdot {\gamma_{t}\left( {11,11} \right)} \cdot {\beta_{t}(11)}} \end{Bmatrix}.}} \end{matrix} & \left\lbrack {{{Eqn}.\mspace{14mu} 16}A} \right\rbrack \end{matrix}$

If the symbol size m is shorter, then the probabilities of all data patterns are added, with the last m bits being the same as the symbol under consideration: For example, for a four state trellis with half rate (k=½) implementation and three bit symbols, the PMFs are computed as follows:

$\begin{matrix} {{{PMF}\left( s_{{({t - 1})}/m} \right)} = {\begin{Bmatrix} {{PMF}(000)}_{t} \\ {{PMF}(001)}_{t} \\ {{PMF}(010)}_{t} \\ {{PMF}(011)}_{t} \\ {{PMF}(100)}_{t} \\ {{PMF}(101)}_{t} \\ {{PMF}(110)}_{t} \\ {{PMF}(111)}_{t} \end{Bmatrix} = {\begin{Bmatrix} {{{\alpha_{t - 2}(00)} \cdot {\gamma_{t - 1}\left( {00,00} \right)} \cdot {\gamma_{t}\left( {00,00} \right)} \cdot {\beta_{t}(00)}} + {{\alpha_{t - 2}(10)} \cdot {\gamma_{t - 1}\left( {10,00} \right)} \cdot {\gamma_{t}\left( {00,00} \right)} \cdot {\beta_{t}(00)}}} \\ {{{\alpha_{t - 2}(00)} \cdot {\gamma_{t - 1}\left( {00,00} \right)} \cdot {\gamma_{t}\left( {00,01} \right)} \cdot {\beta_{t}(01)}} + {{\alpha_{t - 2}(10)} \cdot {\gamma_{t - 1}\left( {10,00} \right)} \cdot {\gamma_{t}\left( {00,01} \right)} \cdot {\beta_{t}(01)}}} \\ {{{\alpha_{t - 2}(00)} \cdot {\gamma_{t - 1}\left( {00,01} \right)} \cdot {\gamma_{t}\left( {01,10} \right)} \cdot {\beta_{t}(10)}} + {{\alpha_{t - 2}(10)} \cdot {\gamma_{t - 1}\left( {10,01} \right)} \cdot {\gamma_{t}\left( {01,10} \right)} \cdot {\beta_{t}(10)}}} \\ {{{\alpha_{t - 2}(00)} \cdot {\gamma_{t - 1}\left( {00,01} \right)} \cdot {\gamma_{t}\left( {01,11} \right)} \cdot {\beta_{t}(11)}} + {{\alpha_{t - 2}(10)} \cdot {\gamma_{t - 1}\left( {10,01} \right)} \cdot {\gamma_{t}\left( {01,11} \right)} \cdot {\beta_{t}(11)}}} \\ {{{\alpha_{t - 2}(01)} \cdot {\gamma_{t - 1}\left( {01,10} \right)} \cdot {\gamma_{t}\left( {10,00} \right)} \cdot {\beta_{t}(00)}} + {{\alpha_{t - 2}(11)} \cdot {\gamma_{t - 1}\left( {11,10} \right)} \cdot {\gamma_{t}\left( {10,00} \right)} \cdot {\beta_{t}(00)}}} \\ {{{\alpha_{t - 2}(01)} \cdot {\gamma_{t - 1}\left( {01,10} \right)} \cdot {\gamma_{t}\left( {10,01} \right)} \cdot {\beta_{t}(01)}} + {{\alpha_{t - 2}(11)} \cdot {\gamma_{t - 1}\left( {11,10} \right)} \cdot {\gamma_{t}\left( {10,01} \right)} \cdot {\beta_{t}(01)}}} \\ {{{\alpha_{t - 2}(01)} \cdot {\gamma_{t - 1}\left( {01,11} \right)} \cdot {\gamma_{t}\left( {11,10} \right)} \cdot {\beta_{t}(10)}} + {{\alpha_{t - 2}(11)} \cdot {\gamma_{t - 1}\left( {11,11} \right)} \cdot {\gamma_{t}\left( {11,10} \right)} \cdot {\beta_{t}(10)}}} \\ {{{\alpha_{t - 2}(01)} \cdot {\gamma_{t - 1}\left( {01,11} \right)} \cdot {\gamma_{t}\left( {11,11} \right)} \cdot {\beta_{t}(11)}} + {{\alpha_{t - 2}(11)} \cdot {\gamma_{t - 1}\left( {11,11} \right)} \cdot {\gamma_{t}\left( {11,11} \right)} \cdot {\beta_{t}(11)}}} \end{Bmatrix}.}}} & \left\lbrack {{{Eqn}.\mspace{14mu} 16}B} \right\rbrack \end{matrix}$

From 1/k rate implementation of a 2^(n) state trellis, the probability of a data pattern of length n+k (corresponding to a single trellis stage of a 1/k rate detector) can be computed starting from time t−n−k+1 ending at time t as follows:

$\begin{matrix} {{{\Pr\left( \left\{ {g_{0},g_{1},\ldots\mspace{14mu},g_{n + k - 1}} \right\}_{t} \right)} = {\Pr\left( {{u_{t - n - k + 1} = g_{0}},\ldots\mspace{14mu},{u_{t - 1} = g_{n + k - 1}}} \right)}}{{\Pr\left( \left\{ {g_{0},g_{1},\ldots\mspace{14mu},g_{n + k - 1}} \right\}_{t} \right)} = {{\alpha_{t - k}\left( S_{t - k}^{g_{n + 1}} \right)} \cdot \left( {\prod\limits_{z = 0}^{k - 1}{\gamma_{t}\left( {S_{t - k + z}^{g_{n + 1 + z}},{f\left( {S_{t - k + z}^{g_{n + 1 + z}},g_{n + 1 + z}} \right)}} \right)}} \right) \cdot {{\beta_{t}\left( S_{t}^{g_{n + k - 1}} \right)}.}}}} & \left\lbrack {{Eqn}.\mspace{14mu} 17} \right\rbrack \end{matrix}$

If n+k=m, then for (t−1)/m^(th) symbol's PMF entry of GF element f₁ is according to Equation 18: PMF(f ₁ ={g ₀ ,g ₁ , . . . ,g _(m−1)}_(t))=Pr({u ₀ =g ₀ ,u ₁ =g ₁ , . . . , u _(n+k−1) =g _(n+k−1)}_(t))  [Eqn. 18].

If the symbol size m<n+k, the PMF can be computed by adding the probabilities of all data patterns with the last m bits the same as the symbol under consideration:

$\quad\begin{matrix} \begin{matrix} {\quad{{{PMF}\left( {f_{1} =}\quad \right.}\left. \quad\left\{ {g_{0},g_{1},\ldots\mspace{14mu},g_{m - 1}} \right\}_{t} \right)}} \\ {= {\underset{u_{0}}{{\quad}{\quad\sum}}\mspace{11mu}\ldots\mspace{14mu}{\sum\limits_{u_{n + k - m - 1}}{\Pr\left( \left\{ {u_{0},\ldots\mspace{14mu},u_{n + k - m - 1},u_{n + k - m}} \right. \right.}}}} \\ {{= g_{0}},\ldots\mspace{14mu},u_{m - 1}} \\ {\left. \left. {= g_{m - 1}} \right\}_{t} \right).} \end{matrix} & \left. \left\lbrack {{Eqn}.\mspace{14mu} 19} \right\rbrack \right\rbrack \end{matrix}$

Table 1 shows a list of supported PMF symbol sizes and the frequency of PMF computation for different detector sizes and implementation rates.

Supported PMF symbol size: m = k · x for x = 0, 1, . . . PMF computation frequency: m/k Number of Full Half rate Quarter states rate (½) ⅓ rate rate (¼)  4 1, 2, 3, 2, 4, 6, 3, 6, 9 . . . 4, 8, . . . 4, 5 . . . 8, . . .  8 1, 2, 3, 2, 4, 6, 3, 6, 9 . . . 4, 8, . . . 4, 5 . . . 8, . . . 16 1, 2, 3, 2, 4, 6, 3, 6, 9 . . . 4, 8, . . . 4, 5 . . . 8, . . . 32 1, 2, 3, 2, 4, 6, 3, 6, 9 . . . 4, 8, . . . 4, 5, 6 8, . . . . . . PMF Every m = 2→ m/k = 1 m = 3→ m/k = 1 m = 4→ m/k = 1 Computation mth m = 4→m/k = 2 m = 6→m/k = 2 m = 8→ m/k = 2 Frequency → stage m = 6→m/k = 3 m = 9→m/k = 3 m = 12→m/k = 3

Supported symbol sizes, denoted bold in Table 1, utilize a single trellis stage of the 1/k rate detector (corresponding to a data pattern of size n+k). For half, third, quarter and higher rate implementations of the detector, symbol sizes that are not multiples of k can be supported as well, provided that the intermediate branch values are stored for processing. That is, for a 1/k rate detector, the transition probabilities corresponding to each of the k transitions are stored. These values are then used to compute the intermediate forward and backward variables which are utilized for PMF computation.

Further, for a symbol size of m, the PMF shows the probabilities of m consecutive bits that make up the symbol. For example, assuming m=3, then PMF₀ shows the joint probabilities of bits (0,1,2), PMF₁ shows the joint probability of bits (3,4,5).

A one bit transition from one state to the next corresponds to data patterns of length (n+k)=(n+1).

“s” trellis stages of a 1/k rate 2^(n) state detector correspond to a data pattern of (n+k.s) because each trellis stage corresponds to k transition bits and states are represented by n bits.

A 1/k rate 2^(n) state detector stages include a granularity of k bits, that is, k bits per transition.

The different rate detectors for supported symbol sizes and PMF computation frequency are:

Full rate detector: For this case, the MAP detector 205 considers one transition at a time, that is, transitions from state S_(t−1) to S_(t) with transition bit u_(t):

$\ldots\mspace{14mu}{S_{t - 1}\overset{u_{t}}{\longrightarrow}S_{t}\overset{u_{t + 1}}{\longrightarrow}S_{t + 1}\overset{u_{t} + 2}{\longrightarrow}S_{t + 2}}\mspace{14mu}\ldots$

As a result, PMF computation is done at every m-th trellis stage. For instance, if m=2, then PMF₀=Pr[u₀u₁] at t=2 which corresponds to two transition bits u₀u₁. Similarly, PMF₁=Pr[u₂u₃] at t=4 which corresponds to two transition bits u₂u₃.

Half rate detector: for this case, the MAP detector 205 considers two transitions at a time, that is, transitions from state S_(t−2) to S_(t) with transition bits u_(t−1) u_(t−2):

$\ldots\mspace{14mu}{S_{t - 2}\overset{u_{t - 1}u_{t}}{\longrightarrow}S_{t}\overset{u_{t + 1}u_{t + 2}}{\longrightarrow}S_{t + 2}\overset{u_{t + 3}u_{t + 4}}{\longrightarrow}S_{t + 4}}\mspace{14mu}\ldots$

In this example, symbol sizes that are multiple of k are supported since the first trellis stage corresponds to transition bits {0,1}, second trellis stage corresponds to bits {2,3} and third trellis stage corresponds to bits {4,5} and i-th trellis stage corresponds to bits {2*i,2*i+1}. Accordingly, the trellis includes steps of two (2). Therefore, a half rate detector only supports symbol sizes that are multiple of two (2).

For example, let's consider m=8 for half rate eight state trellis. For this case, PMF_(k) represents probability of the symbol made of bits {k−7, k−6, . . . , k}. Similarly, the next PMF represents probability of symbols made of bits {k+1, k+2, . . . k+8}. The data patterns for different number of trellis stages are as follows:

Single trellis stage data pattern is for five (5) bits {0,1,2,3,4}.

Two (2) trellis stages' data pattern is for seven (7) bits {0,1, . . . ,5,6}.

Three (3) trellis stages' data pattern is for nine (9) bits {0,1, . . . ,7,8}

To cover the required eight (8) bit symbol size, a three half rate trellis stages is utilized, which correspond to a data pattern size of 3+2*3=9 bits. Therefore, if first PMF is computed from the 3^(rd) trellis stage, the next PMF computation will occur m/k=8/2=4 half rate stages later, that is, at 3+4=7^(th) half rate trellis stage.

⅓ rate and ¼ rate detectors: for these cases, the same arguments given for half rate detector apply.

For a 2^(n) state trellis with 1/k rate implementation, the results in Table 1 can be summarized as follows:

Supported symbol sizes: m=k.x for x=0, 1, . . .

PMF computation frequency: m/k

Any supported symbol size that is greater than n+k requires PMF computation involving more than one 1/k rate trellis stages. Therefore, the transition probabilities are stored for all required stages. Supported symbol sizes: m=k.x for m<n+k and x=0, 1, . . . (Shown bold in Table 1).

In some embodiments, the MAP detector 205 is implemented in the log domain. This transforms the multiplications of all probability terms into additions of the logarithms of the probabilities and the Equation 17 becomes:

$\begin{matrix} {{\log\left( {\Pr\left( \left\{ {g_{0},g_{1},\ldots\mspace{14mu},g_{n + k - 1}} \right\} \right)}_{t} \right)} = {{\log\left( {\alpha_{t - k}\left( S_{t - k}^{g_{n + 1}} \right)} \right)} + \left( {\sum\limits_{z = 0}^{k - 1}{\log\left( {\gamma_{t}\left( {S_{t - k + z}^{g_{n + 1 + z}},{f\left( {S_{t - k + z}^{g_{n + 1 + z}},g_{n + 1 + z}} \right)}} \right)} \right)}} \right) + {{\log\left( {\beta_{t}\left( S_{t}^{g_{n + k - 1}} \right)} \right)}.}}} & \left\lbrack {{Eqn}.\mspace{14mu} 20} \right\rbrack \end{matrix}$

As mentioned earlier, if the symbol size m is shorter than n+k, the PMF is computed by adding the probabilities of all data patterns with the last m bits being the same as the symbol under consideration (such as in Equation 19). For log domain implementation of Equation 19, a Jacobian approximation can be used for the summation of the probabilities: log(p ₁ +p ₂)=max(log(p ₁),log(p ₂))  [Eqn. 21].

This is the same approximation used for max-log-MAP process and this simplification does not cause significant performance degradation. If an exact answer is sought for the logarithm of the PMF given by Equation 19, then a correction term indexed by log(p₁)-log(p₂) is added to Equation 21, which can be costly to implement.

Following Jacobian approximation, Equation 17 becomes Equation 22:

$\begin{matrix} {{\log\left( {{PMF}\left( {f_{1} = \left\{ {g_{0},g_{1},\ldots\mspace{14mu},g_{m - 1}} \right\}_{t}} \right)} \right)} = {\max{\left\{ {\log\left( {\Pr\left( \begin{Bmatrix} {u_{0},\ldots\mspace{14mu},u_{n + k - m - 1},{u_{n + k - m} =}} \\ {g_{0},\ldots\mspace{14mu},{u_{m - 1} = g_{m - 1}}} \end{Bmatrix}_{t} \right)} \right)} \right\}.}}} & \left\lbrack {{Eqn}.\mspace{14mu} 22} \right\rbrack \end{matrix}$

In Equation 22, the maximization is done over all combinations of u₀, . . . ,u_(n+k−m−1). Since the symbol based ECC decoder 220 is usually implemented in log domain, log(PMFs) are used, which are computed using Equation 22.

In channel detector 105 (e.g., when a MAP detector), the extrinsic LLR information is used in the branch metric computation γ_(t) ^(x)(S_(t−1) ^(x),S_(t) ^(x)). The branch metric represents the probability of moving from state S_(t−1) ^(x) and to state S_(t) ^(x) with transition bit x given the received noisy channel output sequence y. If a-priori information about transition bit x exists, this extrinsic information can be used in the branch metric computation as illustrated in Equation 23: γ_(t) ^(x)(S _(t−1) ^(x) ,S _(t) ^(x))=Pr(y _(t) ,S _(t) ^(x) |S _(t−1) ^(x))·Pr(u _(t) =x)  [Eqn. 23].

If there is no a-priori information about the transition bit, then the multiplication in Equation 23 is not necessary. For the case of turbo equalization, the channel detector 105 and ECC decoder 115 exchange soft information which leads to significant performance improvement. If the ECC 100 is bit based then the ECC decoder 115 computes LLRs, which are directly useable by the detector 105. However, for the case of symbol based ECC 200, the soft decoder 220 computes PMFs. LLRs can be computed from the PMFs, such as in the PMF-to-LLR conversion block 230. Thereafter, the LLRs can be used in the MAP detector 205. However, this approach can decrease the potential turbo equalization gains significantly.

In some embodiments, the MAP detector 205 is configured to utilize ePMF (e.g., extrinsic PMF). The MAP detector 205 can use the ePMF information from the symbol based ECC decoder 220 without computing the LLRs.

The forward and backward variable computations for use by the MAP detector 205 in order to utilize the ePMFs directly are as follows:

Forward variable in a conventional 1/k rate MAP detector is computed according to Equation 24:

$\begin{matrix} {{\alpha_{t}\left( S_{t}^{x = {\lbrack{x_{0}x_{1}\mspace{14mu}\ldots\mspace{14mu} x_{k - 1}}\rbrack}} \right)} = {\sum\limits_{S_{t - k}^{x = {\lbrack{x_{0}x_{1}\mspace{14mu}\ldots\mspace{14mu} x_{k - 1}}\rbrack}}}{{\alpha_{t - k}\left( S_{t - k}^{x_{0}} \right)} \cdot {\left( {\prod\limits_{z = 0}^{k - 1}{\gamma_{t}\left( {S_{t - k + z}^{x_{z}},{f\left( {S_{t - k + z}^{x_{z}},x_{z}} \right)}} \right)}} \right).}}}} & \left\lbrack {{Eqn}.\mspace{14mu} 24} \right\rbrack \end{matrix}$

For full rate implementation (k=1), Equation 16 simplifies to:

$\begin{matrix} {{\alpha_{t}\left( S_{t}^{x} \right)} = {\sum\limits_{S_{t - 1}^{x}}{{\alpha_{t - 1}\left( S_{t - 1}^{x} \right)} \cdot {{\gamma_{t}\left( {S_{t - 1}^{x},S_{t}^{x}} \right)}.}}}} & \left\lbrack {{Eqn}.\mspace{14mu} 25} \right\rbrack \end{matrix}$

In Equations 24 or 25, the extrinsic LLR information is incorporated into transition probability computation shown in Equation 22. For the case of max-log-map, the multiplications in Equations 24 and 25 become additions and the summation is replaced by a max operation.

Furthermore, all paths leading to the destination state in forward variable computation share exact same transition bits. For 1/k rate implementation, the transitions are caused by k transition bits. For example, for a half rate four state trellis, as illustrated in FIG. 5, from all four states with transition bits ‘00,’ a transition is made to state ‘00.’ Similarly, from all four states with transition bits ‘11,’ a transition is made to state ‘11.’

Additionally, since all transitions ending at a destination state have the same transition bits, in Equation 24, the forward variable can be computed without taking a-priori information into account in the γ (transition probability) computation. This binary a-priori information can be included to the computed forward variable as according to Equations 26 and 27:

$\begin{matrix} {{\Pr\left( {\left\lbrack {u_{t - k + 1}\mspace{14mu}\ldots\mspace{14mu} u_{t}} \right\rbrack = \left\lbrack {x_{0}\mspace{14mu}\ldots\mspace{14mu} x_{k - 1}} \right\rbrack} \right)} = {\left( {\prod\limits_{z = 0}^{k - 1}{\Pr\left( {u_{t - z} = x_{k - 1 - z}} \right)}} \right).}} & \left\lbrack {{Eqn}.\mspace{14mu} 26} \right\rbrack \\ {{\alpha_{t}\left( S_{t}^{x = {\lbrack{x_{0}x_{1}\mspace{14mu}\ldots\mspace{14mu} x_{k - 1}}\rbrack}} \right)} = {\quad{\left\lbrack {\sum\limits_{S_{t}^{x = {\lbrack{x_{0}x_{1}\mspace{14mu}\ldots\mspace{14mu} x_{k - 1}}\rbrack}}}{{\alpha_{t - k}\left( S_{t - k}^{x_{0}} \right)} \cdot \left( {\prod\limits_{z = 0}^{k - 1}{\gamma_{t}\left( {S_{t - k + z}^{x_{z}},{f\left( {S_{t - k + z}^{x_{z}},x_{z}} \right)}} \right)}} \right)}} \right\rbrack \cdot {\quad{{\Pr\begin{pmatrix} {\left\lbrack {u_{t - k + 1}\mspace{14mu}\ldots\mspace{14mu} u_{t}} \right\rbrack =} \\ \left\lbrack {x_{0}\mspace{14mu}\ldots\mspace{14mu} x_{k - 1}} \right\rbrack \end{pmatrix}}.}}}}} & \left\lbrack {{Eqn}.\mspace{14mu} 27} \right\rbrack \end{matrix}$

Equation 26 computes the probability of the k-bit transition sequence. Since PMF represents m bit symbol probability, for k=m the PMF can be used in Equation 27 directly as illustrated in Equation 28:

$\begin{matrix} {{\alpha_{t}\left( S_{t}^{x = {\lbrack{x_{0}x_{1}\mspace{14mu}\ldots\mspace{14mu} x_{k - 1}}\rbrack}} \right)} = {\quad{\left\lbrack {\sum\limits_{S_{t}^{x = {\lbrack{x_{0}x_{1}\mspace{14mu}\ldots\mspace{14mu} x_{k - 1}}\rbrack}}}{{\alpha_{t - k}\left( S_{t - k}^{x_{0}} \right)} \cdot \left( {\prod\limits_{z = 0}^{k - 1}{\gamma_{t}\left( {S_{t - k + z}^{x_{z}},{f\left( {S_{t - k + z}^{x_{z}},x_{z}} \right)}} \right)}} \right)}} \right\rbrack \cdot {{{PMF}\left( {x_{0}x_{1}\mspace{14mu}\ldots\mspace{14mu} x_{k - 1}} \right)}_{t}.}}}} & \left\lbrack {{Eqn}.\mspace{14mu} 28} \right\rbrack \end{matrix}$

For example, when the MAP detector 205 is a half rate (i.e., k=2), four state detector and the decoder 220 is a two bit symbol based ECC (i.e., m=2, GF(2)), the forward variable can be computed according to Equations 29A-29D:

$\begin{matrix} {{\alpha_{t}(00)} = {\begin{pmatrix} {{{\alpha_{t - 2}(00)} \cdot {\gamma_{t - 1}\left( {00,00} \right)} \cdot {\gamma_{t}\left( {00,00} \right)}} + {{\alpha_{t - 2}(01)} \cdot}} \\ {{{\gamma_{t - 1}\left( {01,10} \right)} \cdot {\gamma_{t}\left( {10,00} \right)}} + {{\alpha_{t - 2}(10)} \cdot {\gamma_{t - 1}\left( {10,00} \right)} \cdot}} \\ {{\gamma_{t}\left( {00,00} \right)} + {{\alpha_{t - 2}(11)} \cdot {\gamma_{t - 1}\left( {11,10} \right)} \cdot {\gamma_{t}\left( {10,00} \right)}}} \end{pmatrix} \cdot {{{PMF}(00)}_{t}.}}} & \left\lbrack {{{Eqn}.\mspace{14mu} 29}A} \right\rbrack \\ {{\alpha_{t}(01)} = {\begin{pmatrix} {{{\alpha_{t - 2}(00)} \cdot {\gamma_{t - 1}\left( {00,00} \right)} \cdot {\gamma_{t}\left( {00,01} \right)}} + {{\alpha_{t - 2}(01)} \cdot}} \\ {{{\gamma_{t - 1}\left( {01,10} \right)} \cdot {\gamma_{t}\left( {10,01} \right)}} + {{\alpha_{t - 2}(10)} \cdot {\gamma_{t - 1}\left( {10,00} \right)} \cdot}} \\ {{\gamma_{t}\left( {00,01} \right)} + {{\alpha_{t - 2}(11)} \cdot {\gamma_{t - 1}\left( {11,10} \right)} \cdot {\gamma_{t}\left( {10,01} \right)}}} \end{pmatrix} \cdot {{{PMF}(01)}_{t}.}}} & \left\lbrack {{{Eqn}.\mspace{14mu} 29}B} \right\rbrack \\ {{\alpha_{t}(10)} = {\begin{pmatrix} {{{\alpha_{t - 2}(00)} \cdot {\gamma_{t - 1}\left( {00,01} \right)} \cdot {\gamma_{t}\left( {01,10} \right)}} + {{\alpha_{t - 2}(01)} \cdot}} \\ {{{\gamma_{t - 1}\left( {01,11} \right)} \cdot {\gamma_{t}\left( {11,01} \right)}} + {{\alpha_{t - 2}(10)} \cdot {\gamma_{t - 1}\left( {10,01} \right)} \cdot}} \\ {{\gamma_{t}\left( {01,10} \right)} + {{\alpha_{t - 2}(11)} \cdot {\gamma_{t - 1}\left( {11,11} \right)} \cdot {\gamma_{t}\left( {10,10} \right)}}} \end{pmatrix} \cdot {{{PMF}(10)}_{t}.}}} & \left\lbrack {{{Eqn}.\mspace{14mu} 29}C} \right\rbrack \\ {{\alpha_{t}(11)} = {\begin{pmatrix} {{{\alpha_{t - 2}(00)} \cdot {\gamma_{t - 1}\left( {00,01} \right)} \cdot {\gamma_{t}\left( {01,11} \right)}} + {{\alpha_{t - 2}(01)} \cdot}} \\ {{{\gamma_{t - 1}\left( {01,11} \right)} \cdot {\gamma_{t}\left( {11,11} \right)}} + {{\alpha_{t - 2}(10)} \cdot {\gamma_{t - 1}\left( {10,01} \right)} \cdot}} \\ {{\gamma_{t}\left( {01,11} \right)} + {{\alpha_{t - 2}(11)} \cdot {\gamma_{t - 1}\left( {11,11} \right)} \cdot {\gamma_{t}\left( {11,11} \right)}}} \end{pmatrix} \cdot {{{PMF}(11)}_{t}.}}} & \left\lbrack {{{Eqn}.\mspace{14mu} 29}D} \right\rbrack \end{matrix}$

For max-log-map algorithm, the multiplications in the above example become additions and the summation term before PMF multiplication is replaced by a max operation.

Therefore, for GF(2^(m)) ECC code and a 1/k rate MAP detector 205, the extrinsic PMF from the ECC decoder 220 is easily used for the forward variable computation of the MAP detector 205

by simply multiplying the computed forward variable with a relevant PMF entry.

In Table 2, for different rate and state detectors, the supported PMF symbol sizes are shown. A 1/k rate MAP detector 205 covers symbol sizes that are multiples of k. The MAP detector 205 can multiply the computed forward variable with a relevant PMF entry.

For example, with a half rate eight state trellis and a symbol size of m=8, the PMF_(k) represents probability of the symbol made of bits {k−7,k−6, . . . ,k}. Similarly the next PMF represents probability of symbols made of bits {k+1,k+2, . . . k+8}. Therefore, when computing the first PMF from the 3^(rd) trellis stage, the next PMF computation will be performed (m/k)=(8/2)=4 half rate stages later, that is, at a 3+4=7th half rate trellis stage.

In another example, the MAP detector 205 is a quarter rate detector including only two bit symbols. Each trellis stage corresponds to four transition bits. The computed forward variable is multiplied with the probability of the four bit transition sequence. Since two bit symbols are included, the transition sequence probability is computed by multiplying two appropriate PMFs as illustrated in Equations 30A and 30B: Pr(x ₀=1,x ₁=0,x ₂=1,x ₃=1)=PMF(1011)₀  [Eqn. 30A]. Pr(x ₀=1,x ₁=0,x ₂=1,x ₃=1)=PMF(10)₀·PMF(11)₀  [Eqn. 30B].

For supported symbol sizes in Table 2 that are smaller than the number of transition bits per trellis stage (k), the transition bit sequence probability is computed by multiplying k/m appropriate PMF values.

TABLE 2 Supported PMF symbol sizes for using extrinsic PMF in forward variable computation. Supported PMF symbol sizes, m = k · x for x = 0, 1, . . . PMF computation frequency: max (1, m/k) Number of Full rate Half rate (½) ⅓ rate Quarter rate (¼) states k = 1 k = 2 k = 3 k = 4  4 1, 2, 3, 4, 1, 2, 4, 6, 1, 3, 6, . . . 1, 2, 4, 8, 5 . . . . . . . . .  8 1, 2, 3, 4, 1, 2, 4, 6, 1, 3, 6, . . . 1, 2, 4, 8, 5 . . . . . . . . . 16 1, 2, 3, 4, 1, 2, 4, 6, 1, 3, 6, . . . 1, 2, 4, 8, 5 . . . . . . . . . 32 1, 2, 3, 4, 1, 2, 4, 6, 1, 3, 6, . . . 1, 2, 4, 8, 5, 6 . . . . . . . . . Computation Every m = 1→ 1 m = 1→ 1 m = 1→ 1 Frequency mth m = 2→ m/k = 1 m = 3→ m/k = 1 m = 2→ 1 → stage m = 4→m/k = 2 m = 6→m/k = 2 m = 4→ m/k = 1 m = 6→m/k = 3 m = 9→m/k = 3 m = 8→ m/k = 2

In Table 2, the supported symbol sizes, denoted bold, utilize single trellis stages of the MAP detector 205.

The MAP detector 205 also can perform backward variable computation with ePMF Information. The MAP detector 205 can compute the backward variable according to Equation 31:

$\begin{matrix} {{\beta_{t}\left( S_{t}^{x = {\lbrack{x_{0}x_{1}\mspace{14mu}\ldots\mspace{14mu} x_{k - 1}}\rbrack}} \right)} = {\sum\limits_{S_{t}^{x = {\lbrack{x_{0}x_{1}\mspace{14mu}\ldots\mspace{14mu} x_{k - 1}}\rbrack}}}{{\beta_{t + k}\left( S_{t + k}^{x_{k - 1}} \right)} \cdot {\left( {\prod\limits_{z = 0}^{k - 1}{\gamma_{t}\left( {S_{t + k + z}^{x_{k - 1 - z}},{f\left( {S_{t + k + z}^{x_{k - 1 - z}},x_{k - 1 - z}} \right)}} \right)}} \right).}}}} & \left\lbrack {{Eqn}.\mspace{14mu} 31} \right\rbrack \end{matrix}$

For full rate implementation (k=1), Equation 31 simplifies to Equation 32:

$\begin{matrix} {{\beta_{t}\left( S_{t}^{x} \right)} = {\sum\limits_{S_{t + 1}^{x}}{{\beta_{t + 1}\left( S_{t + 1}^{x} \right)} \cdot {{\gamma_{t + 1}\left( {S_{t}^{x},S_{t + 1}^{x}} \right)}.}}}} & \left\lbrack {{Eqn}.\mspace{14mu} 32} \right\rbrack \end{matrix}$

In Equations 31 or 32, the extrinsic LLR information is incorporated into transition probability computation shown in Equation 23. For max-log-map detector, the multiplications in Equations 31 and 32 become additions and the summation is replaced by a max operation.

When the MAP detector 205 is configured to use ePMF information, the forward variable computation approach is not used for backward variable computation because all paths merging in the destination state for backward variable computation have different transition bits. For example in a ½ rate 4 state trellis, as illustrated in FIG. 7, at state ‘00’ 702 at time instant t, four incoming paths exist, originating from states ‘00’ 704, ‘01’ 706, ‘10’ 708 and ‘11’ 710 at time instant t+2. The transition bits are ‘00’ 712, ‘01’ 714, ‘10’ 716 and ‘11’ 718 respectively.

The MAP detector 205 utilizes ePMF in backward variable computation by multiplying the transition probability of each path ending at a destination state with an appropriate PMF value. For symbol size of m and detector implementation rate of k, if m=k.x (x=1, 2, 3, . . . ), x trellis stages are evaluated at a time and the combined transition probability is multiplied with the appropriate PMF entry.

For example, assuming m=6, k=½ and n=3, with transition bits ‘011001’ cause a transition from a state ‘000’ to state ‘001’ via states ‘001’ and ‘110’ after 3 half rate transitions. For this transition sequence, one of the summation terms in Equation 31 (corresponding to one of the possible paths ending at state ‘000’) will be: γ_(t)(000,001)⁰¹·γ_(t+2)(001,110)¹⁰·γ_(t+4)(110,001)⁰¹·β_(t+4)(001).

Above, the superscripts denote the transition bits and each transition probability is also a multiplication of two full rate trellis stage probabilities as illustrated in Equation 33: γ_(t) (000,001)⁰¹=γ_(t)(000,000)⁰·γ_(t+1)(000,001)¹  [Eqn. 33].

In this example, the PMF is included into backward variable computation as follows: γ_(t)(000,001)⁰¹·γ_(t+2)(001,110)¹⁰·γ_(t+4)(110,001)⁰¹·β_(t+4)(001)·PMF(011001)_(t+4)

This approach can be generalized according to Equation 34:

$\begin{matrix} {{\beta_{t}\left( S_{t}^{x = {\lbrack{x_{0}x_{1}\mspace{14mu}\ldots\mspace{14mu} x_{k - 1}}\rbrack}} \right)} = {\sum\limits_{S_{t}^{x = {\lbrack{x_{0}x_{1}\mspace{14mu}\ldots\mspace{14mu} x_{k - 1}}\rbrack}}}{{\beta_{t + k}\left( S_{t + k}^{x_{k - 1}} \right)} \cdot {{PMF}\left( {x_{k - m}\mspace{14mu}\ldots\mspace{14mu} x_{k - 1}} \right)}_{t + k} \cdot {\left( {\prod\limits_{z = 0}^{k - 1}{\gamma_{t}\left( {S_{t + k + z}^{x_{k - 1 - z}},{f\left( {S_{t + k + z}^{x_{k - 1 - z}},x_{k - 1 - z}} \right)}} \right)}} \right).}}}} & \left\lbrack {{Eqn}.\mspace{14mu} 34} \right\rbrack \end{matrix}$

In one illustrative example, the MAP detector 205 is a 1/k rate 2^(n) state detector for m bit symbols. The MAP detector 205 is configured to use the ePMF information in a backward variable computation, where m=k and n=m. For example, first the backward variables at time t+k are updated according to Equation 35: β_(t+k)(S _(t+k) =[x ₀ x ₁ . . . x _(n−1)])=β_(t+k)(S _(t+k) =[x ₀ x ₁ . . . x _(n−1)])·PMF_(t+k)([x ₀ x ₁ . . . x _(k−1)])  [Eqn. 35].

The backward variable is then computed according to Equation 31.

When the MAP detector 205 is a half rate (k=2) rate, four state detector and the soft decoder 215 is a two bit symbol based ECC (i.e., m=2, GF(4)), the backward variable is computed as according to Equations 36A-36D:

$\begin{matrix} {{\beta_{t}(00)} = {\begin{pmatrix} {{{\beta_{t + 2}(00)} \cdot {{PMF}_{t + 2}(00)} \cdot {\gamma_{t + 1}\left( {00,00} \right)} \cdot {\gamma_{t + 2}\left( {00,00} \right)}} +} \\ {{{\beta_{t + 2}(01)} \cdot {{PMF}_{t + 2}(01)} \cdot {\gamma_{t + 1}\left( {00,00} \right)} \cdot {\gamma_{t + 2}\left( {00,01} \right)}} +} \\ {{{\beta_{t + 2}(10)} \cdot {{PMF}_{t + 2}(10)} \cdot {\gamma_{t + 1}\left( {00,01} \right)} \cdot {\gamma_{t + 2}\left( {01,10} \right)}} +} \\ {{\beta_{t + 2}(11)} \cdot {{PMF}_{t + 2}(11)} \cdot {\gamma_{t + 1}\left( {00,01} \right)} \cdot {\gamma_{t + 2}\left( {01,11} \right)}} \end{pmatrix} \cdot}} & \left\lbrack {{{Eqn}.\mspace{14mu} 36}A} \right\rbrack \\ {{\beta_{t}(01)} = {\begin{pmatrix} {{{\beta_{t + 2}(00)} \cdot {{PMF}_{t + 2}(00)} \cdot {\gamma_{t + 1}\left( {01,10} \right)} \cdot {\gamma_{t + 2}\left( {10,00} \right)}} +} \\ {{{\beta_{t + 2}(01)} \cdot {{PMF}_{t + 2}(01)} \cdot {\gamma_{t + 1}\left( {01,10} \right)} \cdot {\gamma_{t + 2}\left( {10,01} \right)}} +} \\ {{{\beta_{t + 2}(10)} \cdot {{PMF}_{t + 2}(10)} \cdot {\gamma_{t + 1}\left( {01,11} \right)} \cdot {\gamma_{t + 2}\left( {11,10} \right)}} +} \\ {{\beta_{t + 2}(11)} \cdot {{PMF}_{t + 2}(11)} \cdot {\gamma_{t + 1}\left( {01,11} \right)} \cdot {\gamma_{t + 2}\left( {11,11} \right)}} \end{pmatrix}.}} & \left\lbrack {{{Eqn}.\mspace{14mu} 36}B} \right\rbrack \\ {{\beta_{t}(10)} = {\begin{pmatrix} {{{\beta_{t + 2}(00)} \cdot {{PMF}_{t + 2}(00)} \cdot {\gamma_{t + 1}\left( {10,00} \right)} \cdot {\gamma_{t + 2}\left( {00,00} \right)}} +} \\ {{{\beta_{t + 2}(01)} \cdot {{PMF}_{t + 2}(01)} \cdot {\gamma_{t + 1}\left( {10,00} \right)} \cdot {\gamma_{t + 2}\left( {00,01} \right)}} +} \\ {{{\beta_{t + 2}(10)} \cdot {{PMF}_{t + 2}(10)} \cdot {\gamma_{t + 1}\left( {10,01} \right)} \cdot {\gamma_{t + 2}\left( {01,10} \right)}} +} \\ {{\beta_{t + 2}(11)} \cdot {{PMF}_{t + 2}(11)} \cdot {\gamma_{t + 1}\left( {10,01} \right)} \cdot {\gamma_{t + 2}\left( {01,11} \right)}} \end{pmatrix}.}} & \left\lbrack {{{Eqn}.\mspace{14mu} 36}C} \right\rbrack \\ {{\beta_{t}(11)} = {\begin{pmatrix} {{{\beta_{t + 2}(00)} \cdot {{PMF}_{t + 2}(00)} \cdot {\gamma_{t + 1}\left( {11,10} \right)} \cdot {\gamma_{t + 2}\left( {10,00} \right)}} +} \\ {{{\beta_{t + 2}(01)} \cdot {{PMF}_{t + 2}(01)} \cdot {\gamma_{t + 1}\left( {11,10} \right)} \cdot {\gamma_{t + 2}\left( {10,01} \right)}} +} \\ {{{\beta_{t + 2}(10)} \cdot {{PMF}_{t + 2}(10)} \cdot {\gamma_{t + 1}\left( {11,11} \right)} \cdot {\gamma_{t + 2}\left( {11,10} \right)}} +} \\ {{\beta_{t + 2}(11)} \cdot {{PMF}_{t + 2}(11)} \cdot {\gamma_{t + 1}\left( {11,11} \right)} \cdot {\gamma_{t + 2}\left( {11,11} \right)}} \end{pmatrix}.}} & \left\lbrack {{{Eqn}.\mspace{14mu} 36}D} \right\rbrack \end{matrix}$

In this example, Equation 34 is repeated at every 1/k rate trellis stage, i.e., m/k frequency shown in the previous stages is valid for backward variable computation as well.

In some embodiments, the channel detector 205 is a SOVA detector (hereinafter referred to as SOVA detector 205). SOVA detector 205 can be used as the channel detector for ISI channels. SOVA detector 205 can perform the same processes as discussed for MAP detector 205 to generate PMF and use extrinsic PMF (ePMF).

FIG. 8 illustrates a process for error correction coding according to embodiments of the present disclosure. The embodiment of the process 800 shown in FIG. 8 is for illustration only. Other embodiments could be used without departing from the scope of this disclosure.

In block 805, the channel detector 205 receives a stream of bits with inter-symbol-interference. The channel detector 205 commences an operation to recover the bits in block 810. The channel detector 205 generates extrinsic PMF information in block 815. This PMF information is input to the symbol-based decoder 220, such as a Q'ary LDPC. In block 820, the symbol-based decoder 215 performs an error correction code operation based on the extrinsic PMF information from the channel detector 205. The symbol-based decoder 220 generates and outputs full PMF information in block 825. The full PMF information is used to make hard decisions. Additionally, in block 830, the symbol-based decoder 220 generates extrinsic PMF information to be delivered to the channel detector 205 for the next iteration in a turbo equalization process. The extrinsic PMF information is generated by removing the extrinsic PMF information input to the symbol-based ECC decoder 220 from the full PMF computed by the symbol-based ECC decoder 220.

FIGS. 9A through 9B illustrate devices capable of error correction decoding according to embodiments of the present disclosure. The embodiments of the devices shown in FIGS. 9A through 9B is for illustration only. Other embodiments could be used without departing from the scope of this disclosure.

The symbol based ECC device 900 can include the same structure and functionality as the symbol-based iterative device 200, illustrated in FIG. 2. The symbol based ECC device 900 can include a channel detector and symbol-based decoder (not specifically illustrated in FIGS. 9A and 9B). One or more types of devices or systems can include the symbol based ECC device 900. Additionally, one or more components in the symbol based ECC device 900 can be located in separate controllers within an apparatus or system. In some embodiments, the symbol based ECC device 900 includes the write path 300. In some embodiments, the write path is disposed in a controller separate from the symbol based ECC device 900.

In some embodiments, a symbol based ECC device 900 can be included in a transceiver or receiver of a base station 905 and a transceiver or receiver mobile station 910. The base station 905 and mobile station 910 each transmit and receive communications via a wireless communication channel. For example, the base station 905 can include a transceiver 907 that includes symbol-based ECC device 900. The symbol-based ECC device 900 further includes write path 300 (not specifically illustrated) to encode communications for the mobile stations 910. The base station 905 transmits the encoded communications to the mobile station 910. The mobile station can include a receiver 912 coupled to an antenna 914. The receiver 912 can include the symbol based ECC device 900. The mobile station 910 can receive the communications from the base station 905 over the wireless communication channel 915. The symbol based ECC device 900 recovers the ISI symbols and performs symbol-based soft decision decoding.

Additionally, the symbol based ECC 900 can be included in a computer 920 that reads data from a magnetic communication medium 925. The computer 920 includes a magnetic drive apparatus 930. The magnetic drive apparatus 930 includes the symbol-based iterative device 900 and the write path 300. In some embodiments, the symbol-based iterative device 900 and the write path 300 are disposed in separate components (not illustrated) within the computer 920. The magnetic drive apparatus 930 is configured to read data from the magnetic communication medium 925. The magnetic drive apparatus 930 recovers the symbols and performs symbol-based soft decision decoding. In some embodiments, the magnetic drive apparatus 930 can write data to the magnetic communication medium 925.

In some embodiments, the communication medium 925 is an optical communication medium. In such embodiments, the computer 920 includes an ECC device 900 configured to recover symbols from an optic channel. Additionally, embodiments using different communication channels could be used without departing from the scope of this disclosure.

Although the present disclosure has been described with an exemplary embodiment, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims. 

What is claimed is:
 1. A system for decoding data, the system comprising: a symbol based error correction code magnetic drive device, the error correction code magnetic drive device comprising: a channel detector configured to recover inter-symbol interference (ISI) channel inputs for bits received by the error correction code magnetic drive device and to generate first extrinsic probability mass function (PMF) information; and a symbol-based decoder coupled to the channel detector and configured to receive the first extrinsic PMF information from the channel detector, the decoder configured to use the first extrinsic PMF information to perform an error correction code operation on symbols recovered from the received bits, and wherein the decoder is configured to generate full PMF information using the first extrinsic PMF information and to generate second extrinsic PMF information for use by the channel detector.
 2. The system as set forth in claim 1, wherein the channel detector is one of: a maximum-a-posteriori (MAP) detector; and a max-log-MAP.
 3. The system as set forth in claim 1, wherein the channel detector is a soft output Viterbi algorithm (SOVA) detector.
 4. The system as set forth in claim 1, wherein the decoder is configured to create the second extrinsic PMF information by removing input of the first extrinsic PMF information from the full PMF computed by the decoder.
 5. The system as set forth in claim 1, wherein the channel detector is configured to receive the second extrinsic PMF information from the decoder and to use the second extrinsic PMF information in a turbo equalization operation.
 6. The system as set forth in claim 1, further comprising a symbol-based interleaver coupled to an output of the decoder, the symbol-based interleaver configured to interleave the PMF information.
 7. The system as set forth in claim 1, further comprising a symbol based inverse interleaver coupled to the output of the channel detector, the symbol based inverse interleaver configured to interleave the first extrinsic PMF information generated by the channel detector.
 8. The system as set forth in claim 1, wherein the decoder is a low density parity check (LDPC) decoder.
 9. A magnetic drive apparatus, the apparatus comprising: a detector configured to recover inter-symbol-interference (ISI) channel inputs for bits received by the magnetic drive apparatus and to generate first extrinsic probability mass function (PMF) information based on channel outputs, and wherein the detector further is configured to receive and use second extrinsic PMF information as a-priori information; and a decoder coupled to the channel detector and configured to receive the first extrinsic PMF information from the channel detector, the decoder configured to: perform a symbol-based error correction code operation on symbols recovered from the received bits using the first extrinsic PMF information, generate full PMF information using the first extrinsic PMF information, and generate the second extrinsic PMF information for use by the channel detector.
 10. The apparatus as set forth in claim 9, wherein the channel detector is one of: a maximum-a-posteriori (MAP) detector; and a max-log-MAP.
 11. The apparatus as set forth in claim 9, wherein the channel detector is a soft output Viterbi algorithm (SOVA) detector.
 12. The apparatus as set forth in claim 9, wherein the decoder is configured to generate the second extrinsic PMF information by removing input of the first extrinsic PMF information from the full PMF computed by the decoder.
 13. The apparatus as set forth in claim 9, wherein the detector is configured to use the second extrinsic PMF information in a turbo equalization operation.
 14. The apparatus as set forth in claim 9, further comprising a symbol based inverse interleaver coupled to the output of the detector, the symbol based inverse interleaver configured to interleave the first extrinsic PMF information generated by the detector.
 15. The apparatus as set forth in claim 9, wherein the decoder is a low density parity check (LDPC) decoder.
 16. A method for decoding data, the method comprising: receiving bits by a receiver; recovering, by a channel detector, inter-symbol interference (ISI) channel inputs for the received bits; generating, by the channel detector, first extrinsic probability mass function (PMF) information based on channel outputs; performing a symbol based error correction code operation on symbols recovered from the received bits using the first extrinsic PMF information; and generating full PMF information using the first extrinsic PMF information; and generating second extrinsic PMF.
 17. The method as set forth in claim 16, wherein the channel detector is one of: a maximum-a-posteriori (MAP) detector; a max-log-MAP; and a soft output Viterbi algorithm (SOVA) detector.
 18. The method as set forth in claim 16, further comprising: receiving, by the channel detector, the second extrinsic PMF generated by the decoder; and using the second extrinsic PMF in a turbo equalization operation.
 19. The method as set forth in claim 16, further comprising at least one of: inverse interleaving the first PMF information; and symbol interleaving the full PMF information.
 20. The method as set forth in claim 16, wherein performing a symbol based error correction code operation is performed by a low density parity check (LDPC) decoder. 